preliminary two pll programmable clock generator with spread spectrum cy25402 cy25422 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-12565 rev. *a revised march 02, 2007 features ? two fully integrated phase-locked loops (plls) ? input frequency range: ? external crystal: 8 to 48 mhz ? external reference: 8 to 166 mhz clock ? wide operating output frequency range ? 3 to 166 mhz ? programmable spread spectrum modulation frequency range of 30 to 120 khz with lexmark profile ? center spread: 0.125% to 2.5% ? down spread: ?0.25% to ?5% ? frequency select feature with opti on to select four different frequencies ? low-jitter, high-accuracy outputs ? up to three clock outputs ? programmable output drive strength ? glitch-free outputs while frequency switching ? four independent output voltages: 3.3v, 3.0v, 2.5v, and 1.8v ? 8-pin soic package ? commercial and industrial temperature range benefits ? multiple high-performance plls allow synthesis of unrelated frequencies ? nonvolatile programming for customized pll frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ? two spread spectrum capabl e plls with lexmark profile for maximum for emi reduction ? spread spectrum plls can be disabled or enabled separately ? plls can be programmed fo r system frequency margin tests ? meets critical timing requ irements in complex system designs ? suitable for pc, consumer, and networking applications ? ability to synthesize standard frequencies with ease ? application compatibility in standard and low-power systems block diagram osc mux and control logic pll1 (ss) pll2 (ss) output dividers and drive strength control clk3 clk2 clk1 fs1 fs0 sson xout xin pd#/oe
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 2 of 8 general description the cy25402 and cy25422 are two pll programmable spread spectrum clock gener ators used to reduce emi found in high-speed digital electron ic systems. both plls have spread spectrum capability. th e spread spectrum feature are turned on or off using the control pin sson. the advantage of having two plls is that a single device can generate up to two independent frequencies from a single crystal or reference input frequency. generally, a design requires up to two oscillators to achieve the same result with a single cy25402 or cy25422. the device uses cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the input clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies are greatly reduced. this reduction in radiated energy significantly reduces the cost of complying with regulatory agency (emc) requirements and improves time-to-market without degrad ing the system performance. the cy25402 and cy25422 use a factory/field-programmable configuration memory array to provide customization for output frequencies, frequency se lect options, spread charac- teristics like spread percentage and modulation frequency, output drive strength and cr ystal load capacitance. a customized device are configured using cyberclocks tm software or by contacting the factory. the spread percentage is programmed to either center spread or down spread with various spread percentages. the range for center spread is from 0.125% to 2.50%. the range for down spread is from ?0.25% to ?5.0%. contact the factory for smaller or larger spread percentage amounts, if required. the input to the cy25402 and cy25422 is either a crystal or a clock signal. the input frequency range for crystals is 8 mhz to 48 mhz, and for clock si gnals is 8 mhz to 166 mhz. the cy25402 and cy25422 have up to three clock outputs and each output has three possible input sources.there are two frequency select lines fs(1 :0) that provide an option to select four different sets of frequencies among the two plls. each output has programmable output divider options. output 1 has eight possible divider values and outputs 2?3 have four possible divider values for maximum flexibility. the 2 bit or 3 bit output dividers are programmable providing a wide output frequency range. the outputs are glitch-free when frequency is switched using output dividers. the outputs have a predictable phase relationship if the clock source is the same pll and divider values are 2, 3, 4, or 6. the cy25402 and cy25422 are available in an 8-pin soic package with commercial and industrial operating temperature ranges. pin configuration 8 ld soic 1 2 3 4 8 7 6 5 xout gnd clk3/sson pd#/oe/fs1 xin vdd clk1 clk2/fs0 pin description - memory programmable 2-pll device with 2 spread spectrum plls pin number name i/o description 1 xin input crystal or clock input 2 vdd power power supply 3 clk1 output programmable clock output 4 clk2/fs0 output/input programmable clock output or fs0 5 pd#/oe/fs1 input power down, output enable or fs1 6 clk3/sson output/input programm able clock output or sson 7 gnd power power supply ground 8 xout output crystal output table 1. supply voltage options device v dd supply voltage cy25402 cy25422 2.5v, 3.0v or 3.3v 1.8v
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 3 of 8 absolute maximum conditions parameter description condition min. max. unit v dd supply voltage ?0.5 4.5 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? volts ul-94 flammability rating @1/8 in. v-0 msl moisture sensitivity level soic package 1 recommended operating conditions parameter descripti on min. typ. max. unit v dd1 operating voltage, 3.3v 3.0 ? 3.6 v v dd2 operating voltage, 3.0v 2.7 ? 3.3 v v dd3 operating voltage, 2.5v 2.25 ? 2.75 v v dd4 operating voltage, 1.8v 1.65 ? 1.95 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 ? +85 c c load max. load capacitance ? ? 15 pf t pu power-up time for all v dd pins to reach minimum specif ied voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter description conditions min. typ. max. unit v ol output low voltage, all clk pins all v dd levels, i ol = 8 ma 0 ? 0.4 v v oh output high voltage, all clk pins all v dd levels, i oh = ?8 ma v dd ? 0.4 ? v dd v v il all inputs except xin all v dd levels ?0.3 ? 0.2 * v dd v v ih all inputs except xin all v dd levels 0.8 * v dd ?v dd + 0.3 v v ilx input low voltage, clock input to xin pin all v dd levels ?0.3 ? 0.36 v v ihx input high voltage, clock input to xin pin all v dd levels 1.44 ? 2.0 v i ilpdoe input low current, pd#/oe and fs0,1 pins v in = v ss (internal pull up = 100k typical) ??10 a i ihpdoe input high current, pd#/oe and fs0,1 pins v in = v dd (internal pull up = 100k typical) ??1 a i ilsr input low current, sson pin v in = v ss (internal pull down = 100k typical) ??1 a i ihsr input high current, sson pin v in = v dd (internal pull down = 100k typical) ??10 a i dd [1] supply current all clocks running, cl = 0 ??12ma c in input capacitance - all inputs except xin sson, oe, pd# or fs inputs ??7pf note 1. configuration dependent.
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 4 of 8 ac electrical specifications parameter description conditions min. typ. max. unit f in (crystal) crystal frequency 8 ? 48 mhz f in (clock) input clock frequency (xin) 8 ? 166 mhz f out output clock frequency 3 ? 166 mhz dc output duty cycle all clocks except ref out duty cycle is defined in figure 2 ; t 1 /t 2 , 50% of v dd 45 50 55 % dc ref out duty cycle ref in min 45%, max 55% 40 60 % e r clk1-3 rising edge rate v dd = all, 20% to 80% v dd 0.8 ? ? v/ns e f clk1-3 falling edge rate v dd = all, 20% to 80% v dd 0.8 ? ? v/ns t ccj1 cycle-to-cycle jitter configuration dependent. see ta ble 2 ?-?ps t ltj long term jitter configuration dependent. see ta ble 2 ?-?ns t 10 pll lock time ? ? 3 ms table 2. configuration example for jitter reference description max jitter (ps) on output 1(48mhz) max jitter (ps) on output 2 (27 mhz) max jitter (ps) on output 3 (166 mhz) 27mhz t ccj1 155 255 170 27mhz t ltj 770 580 630 48 mhz t ccj1 135 225 100 48 mhz t ltj 535 575 520 recommended crystal specification for smd package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 28 mhz fmax maximum frequency 14 28 48 mhz r1(max) maximum motional resistance (esr) 135 50 30 c0(max) maximum shunt capacitance 4 4 2 pf cl(max) maximum parallel load capacitance 18 14 12 pf dl(max) maximum crystal drive level 300 300 300 w recommended crystal specification for thru-hole package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 24 mhz fmax maximum frequency 14 24 32 mhz r1(max) maximum motional resistance (esr) 90 50 30 c0(max) maximum shunt capacitance 7 7 7 pf cl(max) maximum parallel load capacitance 18 12 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 5 of 8 test and measurement setup figure 1. test and measurement setup voltage and timing definitions figure 2. duty cycle definition figure 3. er = (0.6 x v dd ) /t 3 , ef = (0.6 x v dd ) /t 4 0.1 f v dds outputs c load gnd dut clock output v dd 50% of v dd 0v t 1 t 2 clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 6 of 8 ordering information part number [2] type vdd(v) temperature range lead-free cy25402sxc-xxx 8-pin soic 3.3, 3.0 or 2.5 commercial, 0c to 70c cy25402sxc-xxxt 8-pin soic-tape & reel 3.3, 3.0 or 2.5 commercial, 0c to 70c cy25402fsxc 8-pin soic 3.3, 3.0 or 2.5 commercial, 0c to 70c cy25402fsxc 8-pin soic-tape & reel 3.3, 3.0 or 2.5 commercial, 0c to 70c cy25422sxc-xxx 8-pin soic 1.8 commercial, 0c to 70c cy25422sxc-xxxt 8-pin soic-tape & re el 1.8 commercial, 0c to 70c cy25422fsxc 8-pin soic 1.8 commercial, 0c to 70c cy25422fsxct 8-pin soic-tape & reel 1.8 commercial, 0c to 70c cy25402sxi-xxx 8-pin soic 3.3, 3.0 or 2.5 industrial, -40c to +85c cy25402sxi-xxxt 8-pin soic-tape & reel 3.3, 3.0 or 2.5 industria l, -40c to +85c CY25402FSXI 8-pin soic 3.3, 3.0 or 2.5 industrial, -40c to +85c CY25402FSXIt 8-pin soic-tape & reel 3.3, 3. 0 or 2.5 industrial, -40c to +85c cy25422sxi-xxx 8-pin soic 1.8 ind ustrial, -40c to +85c cy25422sxi-xxxt 8-pin soic-tape & reel 1.8 industrial, -40c to +85c cy25422fsxi 8-pin soic 1.8 industrial, -40c to +85c cy25422fsxit 8-pin soic-tape & reel 1.8 industrial, -40c to +85c note 2. xxx indicates factory programmable are factory programmed config urations. for more details, cont act your local cypress fae or cypress sales representative. f in the part number indicates field pr ogrammable using cyberclocks online software.
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions all products and company names mentioned in this docum ent may be the trademarks of their respective holders. figure 4. 8-lead (150-mil) soic s8 seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c
preliminary cy25402 cy25422 document #: 001-12565 rev. *a page 8 of 8 document history page document title: cy25402/cy25422 two pll programmable clock generator with spread spectrum document number: 001-12565 rev. ecn no. issue date orig. of change description of change ** 690296 see ecn rgl new data sheet *a 815788 see ecn rgl minor change: to post on web
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